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1st IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS'08)
September 29-30, 2008
Cambridge, MA USA

http://ndcs08.arces.unibo.it

Advance Registration Deadline September 12th, 2008!
CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Registration -- Hotel Reservations -- Advance Program -- More Information -- Committees

Scope

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Over the last few years emerging technologies, such as CNT, SET, QCA, spin and molecular electronics, have asserted a prominent role for future innovation in the electronics and computer industry at nanometer scale. Novel computational paradigms (such as quantum and reversible computing) and new manufacturing/fabrication processes (based on DNA-like self-assembly) are being introduced to the technical community. Nano-device, circuit and system implementations for diverse applications are currently being investigated to implement the next generation of electronics and digital computers.
The NDCS Workshop, at its first year, will provide an open forum for presentations in all aspects of design, manufacturing, test and reliability of innovative nano-circuits and systems.

The technical program is available at http://ndcs08.arces.unibo.it/program.htm

The program includes 6 regular sessions with 18 oral presentations.

The sessions cover the following topics: Devices and Assembly, Memories, Magnetic and QCA Computing, QCA Reliability, Testing and Biological Fabrication.

Keynote Speakers
Perspective of Nanotechnology for Information Technnology
Jong-Min Kim,  Samsung Electronics

Invited Speakers
Salvatore Coffa, STMicroelectronics
Key Dates
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Advance Registration Deadline: September 12th, 2008

The Venue
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The Workshop will be held in Cambridge (MA) USA, in an area with one of the highest concentrations of research and academic insitutions in the world.

Registration
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Each accepted paper must have at least one author with a paid full registration (non-student) for the manuscript to be included and published in the proceedings.
The advance registration deadline for prospective attendees is September 12th.


Advance Registration

Reg. Fee

IEEE Members

$400.00

Non-members

$560.00

IEEE Student Members

$320.00

Student Non-members

$400.00

 

Late/On-site Registration

Reg. Fee

IEEE Members

$520.00

Non-members

$728.00

IEEE Student Members

$416.00

Student Non-members

$520.00



Click HERE to to proceed to the online registration website.

Hotel Reservation
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The venue of this year's Workshop is the Hyatt Regency Cambridge, Overlooking Boston

575 Memorial Drive,
Cambridge, Massachusetts, USA 02139-4896
Tel:  +1 617 492 1234     Fax: +1 617 491 6906
Maps & Directions

Minutes from Boston, the Hyatt Regency Cambridge hotel is located along the scenic Charles River overlooking the Boston skyline and is in the midst of two uncommonly exciting cities, Boston and Cambridge.  Each exhibits a unique blend of old world charm coupled with youthful, contemporary sophistication.  Cambridge is the spirit side of Boston and just a bridge away on the historic side.

Room rate for conference attendees is $239 per night.

Advance Program
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Monday -- Tuesday

September 29th, 2008 (Monday)
 
9:00 AM - 10:40 AM OPENING SESSION
9:00 - 9:10

Welcome
General Co-Chairs: Giorgio Baccarani and Fabrizio Lombardi

9:10 - 9:20
Program Introduction
Program Co-Chairs: Cecilia Metra and André DeHon
9:20 - 10:00

Keynote Speaker
Jong-Min Kim (Samsung Electronics)

10:00 - 10:40
Invited Speaker
Salvatore Coffa (STMicroelectronics)
 
10:40 AM - 11:00 AM COFFEE BREAK
 
11:00 AM - 12:00 PM Session 1 - DEVICES AND ASSEMBLY
Chair: Mircea Stan
1.1

Analytical Theory of Graphene Nanoribbon Transistors
Pei Zhao (University of Florida - USA), Mihir Choudhury (Rice University - USA), Kartik Mohanram (Rice University - USA), Jing Guo (University of Florida - USA)

1.2

Effects of channel orientations, high-k gate stacks and stress on UTB-FETs: a QDD simulation study
Luca Silvestri (University of Bologna - Italy), Susanna Reggiani (University of Bologna - Italy), Elena Gnani (University of Bologna - Italy), Antonio Gnudi (University of Bologna - Italy), Massimo Rudan (University of Bologna - Italy), Giorgio Baccarani (University of Bologna - Italy)

1.3

Electomigration feedback controlled Nanogaps fabrication based on MPTMS adhesion layer
Danilo Demarchi (Politecnico di Torino - Italy), Matteo Cocuzza (Politecnico di Torino - Italy), Denis Perrone (Politecnico di Torino - Italy), Pierluigi Civera (Politecnico di Torino - Italy), Gianluca Piccinini (Politecnico di Torino - Italy)

 
12:00 PM - 1:30 PM LUNCH
 

1:30PM - 2:30 PM

Session 2 - MEMORIES
Chair: Iris Bahar
2.1

A Highly-Stable Nanometer Memory for Low-Power Design
Yong-Bin Kim (Northeastern University - USA), Sheng Lin ( Northeastern University - USA)

2.2

Resistive Crossbar Switching Networks to Implement Inherently Fault Tolerant Nano LUTs
Xiaojun Ma (Northeastern University - USA), Jing Huang (Northeastern University - USA), Federica Chiminazzo (University of Bologna - Italy), Daniele Rossi (University of Bologna - Italy), Cecilia Metra (Università di Bologna - Italy), Fabrizio Lombardi (Northeastern University - USA)

2.3

Low Power 8T SRAM using 32nm independent Gate FinFET Technology
Young Bok Kim (Northeastern University - USA), Yong-Bin Kim (Northeastern University - USA), Fabrizio Lombardi (Northeastern University - USA)

 
2:30 PM - 3:00 PM COFFEE BREAK
 
3:00 PM - 4:00 PM Session 3 - MAGNETIC AND QCA COMPUTING
Chair: Bernard Courtis
3.1

Direct Quadratic Minimization using Magnetic Field-based Computing
Sudeep Sarkar (University of South Florida - USA), Sanjukta Bhanja (University of South Florida - USA)

3.2

Design tradeoffs for improved performance in Magnetic QCA-based systems
Michael Niemier (University of Notre Dame - USA), Aaron Dingler (University of Notre Dame - USA), X. Sharon Hu (University of Notre Dame - USA)

3.3

Programmable Comparators Based Array for Regular QCA Implementation
Vladimir Ostrovsky (Tel Aviv University - Israel), Osnat Keren (Bar Ilan University - Israel), Ilya Levin (Tel Aviv University - Israel)

 
September 30th, 2008 (Tuesday)
 
9:00 AM - 10:00 AM Session 4 - QCA RELIABILITY
Chair: Adelio Salsano
4.1

Using Geometric Analysis to Estimate the Yield of Molecular QCA Memory Structures
Timothy J. Dysart (University of Notre Dame - USA), Daniel Lohmer (University of Notre Dame - USA), Peter Kogge (University of Notre Dame - USA)

4.2

Characterization of the Displacement Tolerance of QCA Interconnects
Faizal Karim (University of British Columbia - Canada), Konrad Walus (University of British Columbia - Canada)

4.3

Comparing the Reliability of PLA and Custom Logic Implementations of a QCA Adder
Timothy J. Dysart (University of Notre Dame - USA), Peter Kogge (University of Notre Dame - USA)

 
10:00 AM - 11:00 AM Session 5 - CIRCUIT TESTING
Chair: Vikas Chandra
5.1

Ones Counting Based Error-rate Estimation for Multiple Output Circuits
Zhaoliang Pan (University of Southern California - USA), Melvin Breuer (University of Southern California - USA)

5.2

A BIST Technique for Configurable Nanofabric Arrays
Waleed Al-Assadi (Missouri University of Science and Technology - USA)

5.3

The Case for Logic Scrubbing
André DeHon (University of Pennsylvania - USA)

 
11:00 AM - 11:30 AM COFFEE BREAK
 
11:30 AM - 12:30 PM Session 6 - BIOLOGICAL FABRICATION
Chair: Nicholas Carter
6.1

On the Optimization of DNA Self-Assembly Tile Sets for Nano Manufacturing
Fabrizio Lombardi (Northeastern University - USA), Xiaojun Ma (Northeastern University - USA)

6.2

A Graph Model for Tile Sets in DNA Self-Assembly
Masoud Hashempour (Northeastern University - USA), Zahra Mashreghian Arani (Northeastern University - USA), Fabrizio Lombardi (Northeastern University – USA)

6.3

Accelerated Functional Testing of Digital Microfluidic Biochips
Debasis Mitra (Indian Statistical Institute - India), Sarmishtha Ghoshal (Bengal Engineering & Science University - India), Hafizur Rahaman (Bengal Engg. and Science University, Shibpur - India), Bhargab B. Bhattacharya (Indian Statistical Institute - India), Dwijesh Dutta Majumder (Indian Statistical Institute - India), Krishnendu Chakrabarty (Duke University - USA)

 
12:30 PM - 2:00 PM LUNCH
 
2:00 PM - 3:30 PM PANEL (TBD)
 
More Information
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General Information

Giorgio Baccarani
ARCES-University of Bologna, Italy
Phone: +39 051 2095412
gbaccarani@arces.unibo.it

Fabrizio Lomardi
Northeastern University, USA
Phone: +1 617 373 4854
lombardi@ece.neu.edu

Submission Information

Cecilia Metra
ARCES-University of Bologna, Italy
Phone: +39 051 2093038
cmetra@arces.unibo.it

André DeHon
University of Pennsylvania, USA
Phone: +1 215 573 6090
andre@seas.upenn.edu

Committees
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General co-Chairs
Giorgio Baccarani
ARCES-University of Bologna, Italy
Phone: +39 051 2095412
E-mail:gbaccarani@arces.unibo.it

Fabrizio Lomardi
Northeastern University, USA
Phone: +1 617 373 4854
E-mail:lombardi@ece.neu.edu

Program co-Chairs
Cecilia Metra
ARCES-University of Bologna, Italy
Phone: +39 051 2093038
E-mail:cmetra@arces.unibo.it

André DeHon
University of Pennsylvania, USA
Phone: +1 215 573 6090
E-mail:andre@seas.upenn.edu

Finance Chair
Yong-Bin Kim
Northeastern University, USA
Phone: +1 617 373 2919
E-mail: ybk@ece.neu.edu

Local Arrangements Chair
Martin Margala
University of Massachusetts Lowell, USA
Phone: +1 978-934-2986
E-mail: martin_margala@uml.edu

Publicity Chair
Daniele Rossi
University of Bologna, Italy
Phone: +39 051 2093038
E-mail:d.rossi@unibo.it

Program Committee
Y. Arakawa, University of Tokyo
I. Bahar, Brown University
V. Beiu, UAE University
S. Bhanja, University of South Florida
N. Carter, Intel Corporation
K. Chakrabarty, Duke University
B. Courtois, TIMA
C. Dwyer, Duke University
P. Franzon, NC State
R. Guerrieri, University of Bologna
J. P. Hayes, University of Michigan
N. Jha, Princeton University
B. Kaminska, Simon Fraser University
T. Labean, Duke University
Y. Leblebici, EPFL
W. Lu, University of Michigan
M. Lundstrom, Purdue University
I. Markov, University of Michigan
M. Meyyappan, NASA Ames
S. Mitra, Stanford University
M. Niemier, University of Notre Dame
A. Orailoglu, UC San Diego
S. Reggiani, University of Bologna
K. Roy, Purdue University
M. Rudan, University of Bologna
J. Savage, Brown University
S. Shukla, Virginia Tech
M. Stan, University of Virginia
K. Walus, University of British Columbia
H.-S. P. Wong, Stanford University
A. Zeilinger, University of Vienna

For more information, visit us on the web at: http://ndcs08.arces.unibo.it

The 1st IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS'08) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Doug J. YOUNG
SV Probe Inc.
- USA
Tel.
E-mail dyoung@svprobe.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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